Digital matched filter

ABSTRACT

Consumption power is reduced in a digital matched filter for determining a correlation value between a digital signal (I o ) of 6 bits, which is synchronous with a clock, and a despreading code sequence (C 7  C 6  C 5  C 4  C 3  C 2  C 1  C 0 ) which includes 8 despreading codes. First to eighth flip-flop sets ( 211-218 ) constituting a storage section ( 210 ) are sequentially selected clock by clock by a write selection circuit ( 220 ), and the digital signal (I o ) is stored in the selected flip-flop set. The 8 despreading codes are stored in first to eighth code flip-flops ( 231-238 ), respectively, and are shifted in synchronism with the clock. Output signals of the first to eighth flip-flop sets are multiplied by output signals of the first to eighth code flip-flops in first to eighth multiplication circuits ( 241-248 ), respectively.

TECHNICAL FIELD

The present invention relates to a digital matched filter, and moreparticularly to a digital matched filter suitable for use as acorrelation detector which performs correlation detection of a spectrumspread signal in a portable telephone or the like.

BACKGROUND ART

In a spectrum spread communication based on a code division multiplexaccess (CDMA) system which has been studied for use in the portabletelephone or the like, a matched filter is used when a spectrum spreadsignal is demodulated to an original narrow-band signal (for example,“LSI, 110 mw for Digital Portable Telephone CDMA and Reduction ofConsumption Power”, Nikkei Electronics, No. 656, pp. 14-15, February,1996).

FIG. 1 is a block diagram showing a conventional example of aneight-times spread 8-order digital matched filter constructed by using aFIR digital filter (for example, “Spectrum Spread Handbook Edition No.4”, Stanford Telecom Inc., 1996). A transfer function H(z) of thisdigital matched filter is expressed by the following equation.

H(z)=C ₀ +C ₁ Z ⁻¹ +C ₂ Z ⁻² +C ₃ Z ⁻³ ++C ₄ Z ⁻⁴ +C ₅ Z ⁻⁵ +C ₆ Z ⁻⁶ +C₇ Z ⁻⁷  (1)

This digital matched filter comprises a signal input terminal 1, a clockinput terminal 2, a tapped shift register 10 including first to seventhflip-flop sets 11-17, first to eighth multipliers 21-28, first toseventh adders 31-37, and an output terminal 5. Here, each of the firstto seventh flip-flop sets 11-17 constituting the tapped shift register10 includes 6 flip-flops connected in parallel to each other.

A digital signal I_(o) generated by sampling an analog signal (forexample, a spectrum spread signal) at a sampling frequency of 4.096 MHzis inputted to the signal input terminal 1. The digital signal I_(o) isa 6-bit digital signal in terms of two's complement that is synchronouswith a clock CLK of 4.096 MHz inputted to the clock input terminal 2.The digital signal I_(o) is applied to the first flip-flop set 11 of thetapped shift register 10, and then is sequentially shifted from thefirst flip-flop set 11 toward the seventh flip-flop set 17 insynchronism with the clock CLK.

Each of the first to eighth multipliers 21-28 is a multiplier for 6bits×1 bit, and outputs an output signal of 6 bits. In the firstmultiplier 21, multiplication of the digital signal I_(o) (6 bits) by adespreading code C₀ (1 bit) of an 8-bit despreading code sequence C₇ C₆C₅ C₄ C₃ C₂ C₁ C_(o) is carried out. In the second to eighth multipliers22-28, multiplication operations of output signals of the first toseventh flip-flop sets 11-17 by the despreading codes C₁-C₇ are carriedout, respectively.

For example, when the despreading code indicates “0”, the multiplicationoperations of the digital signal I_(o) and the output signals of thefirst to seventh flip-flop sets 11-17 by “−1” are carried out in themultipliers 21-28, respectively. When the despreading code indicates“1”, the multiplication operations of the digital signal I_(o) and theoutput signals of the first to seventh flip-flop sets 11-17 by “1” arecarried out, respectively. The method of the multiplication operationsin the multipliers 21-28 is not limited to this. For example, when thedespreading code indicates “0”, the multiplication operations of thedigital signal I_(o) and the output signals of the first to seventhflip-flop sets 11-17 by “1” may be carried out, respectively. When thedespreading code indicates “1”, the multiplication operations of thedigital signal I_(o) and the output signals of the first to seventhflip-flops 11-17 by “−1” may be carried out, respectively.

The procedure for the multiplication in each of the multipliers 21-28will be described hereunder with reference to FIG. 2.

In the initial state, all of the output signals of the first to seventhflip-flop sets 11-17 constituting the tapped shift register 10 arerendered to be “0”.

In the first operation state, a first sampling data D₀ of the digitalsignal I_(o) is inputted to the signal input terminal 1, and then themultiplication of the sampling data D₀ by the despreading code C₀ iscarried out in the first multiplier 21. Accordingly, an output signalindicative of a value of D₀×C₀ is outputted from the first multiplier21.

In the second operation state, a second sampling data D₁ of the digitalsignal I_(o) is inputted to the signal input terminal 1 in synchronismwith the clock CLK, and the first sampling data D₀ is fetched in thefirst flip-flop set 11. As a result, the multiplication of the secondsampling data DI by the despreading code C₀ is carried out in the firstmultiplier 21, and the multiplication of the first sampling data D₀ bythe despreading code C₁ is carried out in the second multiplier 22.Accordingly, an output signal indicative of a value of D₁×C₀ isoutputted from the first multiplier 21, and an output signal indicativeof a value of D₀×C₁ is outputted from the second multiplier 22.

In the third operation state, a third sampling data D₂ of the digitalsignal I_(o) is inputted to the signal input terminal 1 in synchronismwith the clock CLK, the first sampling data D₀ is fetched in the secondflip-flop set 12, and the second sampling data D₁ is fetched in thefirst flip-flop set 11. As a result, the multiplication of the thirdsampling data D₂ by the despreading code C₀ is carried out in the firstmultiplier 21, the multiplication of the second sampling data D₁ by thedespreading code C₁ is carried out in the second multiplier 22, and themultiplication of the first sampling data D₀ by the despreading code C₂is carried out in the third multiplier 23. Accordingly, an output signalindicative of a value of D₂×C₀ is outputted from the first multiplier21, an output signal indicative of a value of D₁×C₁ is outputted fromthe second multiplier 22, and an output signal indicative of a value ofD₀×C₂ is outputted from the third multiplier 23. Subsequently, a similaroperation is repeated until a seventh operation state.

In the eighth operation state, an eighth sampling data D₇ of the digitalsignal I_(o) is inputted to the signal input terminal 1 in synchronismwith the clock CLK, and the first to seventh sampling data D₀-D₆ arefetched in the seventh to first flip-flop sets 17-11, respectively.Accordingly, an output signal indicative of a value of D₇×C₀ isoutputted from the first multiplier 21, an output signal indicative of avalue of D₆×C₁ is outputted from the second multiplier 22, an outputsignal indicative of a value of D₅×C₂ is outputted from the thirdmultiplier 23, an output signal indicative of a value of D₄×C₃ isoutputted from the fourth multiplier 24, an output signal indicative ofa value of D₃×C₄ is outputted from the fifth multiplier 25, an outputsignal indicative of a value of D₂×Cs is outputted from the sixthmultiplier 26, an output signal indicative of a value of D₁×C₆ isoutputted from the seventh multiplier 27, and an output signalindicative of a value of D₀×C₇ is outputted from the eighth multiplier28.

Through the above operation, the multiplication operations necessary todetermine a correlation value between the initial 8 sampling data D₀-D₇of the digital signal I_(o) and the 8-bit despreading code sequence C₇C₆ C₅ C₄ C₃ C₂ C₁ C₀ are all carried out.

In the ninth operation state, a ninth sampling data D₈ of the digitalsignal I_(o) is inputted to the signal input terminal 1 in synchronismwith the clock CLK, and the second to eighth sampling data D₁-D₇ arefetched in the seventh to first flip-flop sets 17-11, respectively.Accordingly, an output signal indicative of a value of D₈×C₀ isoutputted from the first multiplier 21, an output signal indicative of avalue of D₇×C₁ is outputted from the second multiplier 22, an outputsignal indicative of a value of D₆×C₂ is outputted from the thirdmultiplier 23, an output signal indicative of a value of D₅×C₃ isoutputted from the fourth multiplier 24, an output signal indicative ofa value of D₄×C₄ is outputted from the fifth multiplier 25, an outputsignal indicative of a value of D₃×C₅ is outputted from the sixthmultiplier 26, an output signal indicative of a value of D₂×C₆ isoutputted from the seventh multiplier 27, and an output signalindicative of a value of D₁×C₇ is outputted from the eighth multiplier28. As a result, the multiplication operations necessary to determine acorrelation value of 8 sampling data D₁-D₈, which are one sampling afterthe initial 8 sampling data D₀-D₇ of the digital signal I_(o), and the8-bit despreading code sequence C₇ C₆ C₅ C₄ C₃ C₂ C₁ C₀ are all carriedout. Subsequently, a similar operation is repeated.

Each of the first to fourth adders 31-34 is an adder for 6 bits+6 bits,and outputs an output signal of 7 bits. Each of the fifth and sixthadders 35 and 36 is an adder for 7 bits+7 bits, and outputs an outputsignal of 8 bits. The seventh adder 37 is an adder for 8 bits+8 bits,and outputs an output signal of 9 bits. In the first adder 31, additionof the output signal (6 bits) of the first multiplier 21 and the outputsignal (6 bits) of the second multiplier 22 is carried out. In thesecond adder 32, addition of the output signal (6 bits) of the thirdmultiplier 23 and the output signal (6 bits) of the fourth multiplier 24is carried out. In the third adder 33, addition of the output signal (6bits) of the fifth multiplier 25 and the output signal (6 bits) of thesixth multiplier 26 is carried out. In the fourth adder 34, addition ofthe output signal (6 bits) of the seventh multiplier 27 and the outputsignal (6 bits) of the eighth multiplier 28 is carried out. In the fifthadder 35, addition of the output signal (7 bits) of the first adder 31and the output signal (7 bits) of the second adder 32 is carried out. Inthe sixth adder 36, addition of the output signal (7 bits) of the thirdadder 33 and the output signal (7 bits) of the fourth adder 34 iscarried out. In the seventh adder 37, addition of the output signal (8bits) of the fifth adder 35 and the output signal (8 bits) of the sixthadder 36 is carried out. As a result, a correlation value MFOUT betweenthe digital signal I_(o) and the despreading code sequence C₇ C₆ C₅ C₄C₃ C₂ C₁ C₀ is obtained in the seventh adder 37, and is outputted to theoutside through the output terminal 5.

Next, a digital matched filter used when a receiving signal isover-sampled will be described.

In a case where the receiving timing is detected by performing thecorrelation detection of the receiving signal in the portable telephoneor the like, in order to improve the accuracy of the receiving timingdetection, the receiving signal is usually m-times over-sampled inrelation to a chip rate frequency, and then is inputted to the matchedfilter. When the receiving signal is doubly over-sampled, a transferfunction H(z) is expressed by the following equation.

H(z)=C ₀ +C ₁ Z ⁻² +C ₂ Z ⁻⁴ +C ₃ Z ⁻⁶ ++C ₄ Z ⁻⁸ +C ₅ Z ⁻¹⁰ +C ₆ Z ⁻¹²+C ₇ Z ⁻¹⁴  (2)

FIG. 3 is a block diagram showing a conventional example of aneight-times spread 16-order digital matched filter constructed by usingan FIR 2-times over-sampling interpolation digital filter. The digitalmatched filter comprises a signal input terminal 101, a clock inputterminal 102, a tapped shift register 110 including first to fourteenthflip-flop sets 111-124, first to eighth multipliers 131-138, first toseventh adders 141-147, and an output terminal 105. Here, each of thefirst to fourteenth flip-flop sets 111-124 constituting the tapped shiftregister 110 includes 6 flip-flops connected in parallel to each other.

A digital signal I_(o) generated by doubly over-sampling an analogsignal (for example, a spectrum spread signal) at a sampling frequencyof 8.192 MHz is inputted to the signal input terminal 101. The digitalsignal I_(o) is a 6-bit digital signal in terms of two's complement thatis synchronous with a clock CLK of 8.192 MHz inputted to the clock inputterminal 102. The digital signal I_(o) is applied to the first flip-flopset 111 of the tapped shift register 110, and then is sequentiallyshifted from the first flip-flop set 111 toward the fourteenth flip-flopset 124 in synchronism with the clock CLK.

Each of the first to eighth multipliers 131-138 is a multiplier for 6bits×1 bit, and outputs an output signal of 6 bits. In the firstmultiplier 131, multiplication of the digital signal I_(o) (6 bits) by adespreading code C₀ (1 bit) of an 8-bit despreading code sequence C₇ C₆C₅ C₄ C₃ C₂ C₁ C₀ is carried out. In the second to eighth multipliers132-138, multiplication operations of output signals of the evenflip-flop sets 112, 114, 116, 118, 120, 122 and 124 of the tapped shiftregister 110 by despreading codes C₁-C₇ are carried out, respectively.

For example, when the despreading code indicates “0”, the multiplicationoperations of the digital signal I_(o) and the output signals of theeven flip-flop sets 112, 114, 116, 118, 120, 122 and 124 by “−1” arecarried out in the multipliers 131-138, respectively. When thedespreading code indicates “1”, the multiplication operations of thedigital signal I_(o) and the output signals of the even flip-flop sets112, 114, 116, 118, 120, 122 and 124 by “1” are carried out,respectively. The method of multiplication in the multipliers 131-138 isnot limited to this. For example, when the despreading code indicates“0”, the multiplication operations of the digital signal I_(o) and theoutput signals of the even flip-flop sets 112, 114, 116, 118, 120, 122and 124 by “1” may be carried out, respectively. When the despreadingcode indicates “1”, the multiplication operations of the digital signalI_(o) and the output signals of the even flip-flop sets 112, 114, 116,118, 120, 122 and 124 by “−1” may be carried out, respectively.

Each of the first to fourth adders 141-144 is an adder for 6 bits+6bits, and outputs an output signal of 7 bits. Each of the fifth andsixth adders 145 and 146 is an adder for 7 bits+7 bits, and outputs anoutput signal of 8 bits. The seventh adder 147 is an adder for 8 bits+8bits, and outputs an output signal of 9 bits. In the first adder 141,addition of the output signal (6 bits) of the first multiplier 131 andthe output signal (6 bits) of the second multiplier 132 is carried out.In the second adder 142, addition of the output signal (6 bits) of thethird multiplier 133 and the output signal (6 bits) of the fourthmultiplier 134 is carried out. In the third adder 143, addition of theoutput signal (6 bits) of the fifth multiplier 135 and the output signal(6 bits) of the sixth multiplier 136 is carried out. In the fourth adder144, addition of the output signal (6 bits) of the seventh multiplier137 and the output signal (6 bits) of the eighth multiplier 138 iscarried out. In the fifth adder 145, addition of the output signal (7bits) of the first adder 141 and the output signal (7 bits) of thesecond adder 142 is carried out. In the sixth adder 146, addition of theoutput signal (7 bits) of the third adder 143 and the output signal (7bits) of the fourth adder 144 is carried out. In the seventh adder 147,addition of the output signal (8 bits) of the fifth adder 145 and theoutput signal (8 bits) of the sixth adder 146 is carried out.

In this digital matched filter, a correlation value MFOUT between thedigital signal I_(o) and the despreading code sequence C₇ C₆ C₅ C₄ C₃ C₂C₁ C₀ is obtained in the seventh adder 147, and is outputted to theoutside through the output terminal 105, too. In the digital matchedfilter, the correlation value MFOUT can be obtained each time that theclock CLK of 8.192 MHz is inputted to the clock input terminal 102, sothat the correlation value MFOUT can be obtained at a time intervalwhich is half the time interval in the digital matched filter shown inFIG. 1.

However, the conventional digital matched filters shown in FIGS. 1 and 3face a fatal problem that consumption power is large. Namely, in theconventional digital matched filter shown in FIG. 1, in order to obtainthe correlation value MFOUT between the digital signal I_(o) and thedespreading code sequence C₇ C₆ C₅ C₄ C₃ C₂ C₁ C₀ the tapped shiftregister 10 including the first to seventh flip-flop sets 11-17 is usedas a tapped delay line unit. As a result, the tapped shift register 10is operated in synchronism with the clock CLK of 4.096 MHz, so thatconsumption power increases. In the conventional digital matched filtershown in FIG. 3, in order to obtain the correlation value MFOUT betweenthe digital signal I_(o) and the despreading code sequence C₇ C₆ C₅ C₄C₃ C₂ C₁ C₀, the tapped shift register 110 including the first tofourteenth flip-flop sets 111-124 is used as a tapped delay line unit.As a result, the tapped shift register 110 is operated in synchronismwith the clock CLK of 8.192 MHz, so that consumption power furtherincreases.

In the correlation detector for the correlation detection of thespectrum spread signal in the portable telephone or the like, thecorrelation detection needs to be carried out for the in-phase channeland the quadrature channel, so that the correlation detector needs to beconstructed by using two of the conventional digital matched filters asabove. As a result, the correlation detector is constructed by using theconventional digital matched filters shown in FIG. 1 or 3, raising aproblem that consumption power in the correlation detector is increased.In addition, there arises a problem that the consumption power in thecorrelation detector increases in proportion to an increase in the bitnumber of digital signal, an increase in the tap number of shiftregister and an increase in the number of interpolation processes.

In order to reduce the consumption power in the correlation detector, amatched filter for wide-band DS-CDMA fundamentally constructed on thebasis of an analog/digital filter for performing the correlationdetection through the analog signal processing has been developed(Sawahashi et al, “Low Power Consumption Matched Filter LSI for WidebandDS-CDMA”, Technical Study Report of the Institute of ElectronicInformation Communication (Radio Communication), RCS95-120, January,1996). The matched filter for wide-band DS-CDMA, however, uses a tappeddelay unit including a plurality of sample-hold circuits inputted withan analog input signal, and a plurality of multiplication circuits forperforming multiplication operations of respective output signals of thetapped delay unit by a multiplicator represented by a digital signal.Therefore, in a utilization such as the portable telephone of thespectrum spread communication system in which the digital signalprocessing predominantly proceeds, a digital matched filter which istotally constructed with digital circuits can be integrated more easilywith peripheral circuits for digital signal processing.

Also, U.S. Pat. No. 5,396,446 discloses a digital filter circuitcomprising a plurality of hold circuits which are respectively inputtedwith an input signal, a recursive tapped shift register for storingmultiplicators, a plurality of multipliers for multiplying outputsignals of the plurality of hold circuits by output signals of therecursive tapped shift register, respectively, and an adder for addingoutput signals of the plurality of multipliers. However, the digitalfilter circuit is not devised with the aim of reducing consumption poweras compared to the conventional digital matched filter using the tappedshift register as the tapped delay unit, but is devised with the aim ofsuppressing the hold error to a minimum by constructing the hold circuitthrough the use of two differential amplifiers, two transistors and twocapacitors and controlling conduction/non-conduction of the twotransistors with clocks which are in opposite phase with each other.Further, in the digital filter circuit, input data is cumulated and heldin the capacitor of each hold circuit, so that the accuracy of holdingthe input data is degraded as compared to a case where input data isheld by a digital circuit. Further, in the digital filter circuit, thehold circuit, the multiplier and the adder are constructed by usinganalog elements such as capacitors. Therefore, in the utilization suchas the portable telephone of the spectrum spread communication system inwhich the digital signal processing predominantly proceeds, the digitalmatched filter which is totally constructed with digital circuits can beintegrated more easily with peripheral circuits for digital signalprocessing.

SUMMARY OF THE INVENTION

An object of the present invention is to provide a digital matchedfilter which can be reduced in consumption power and which can be easilyfabricated in the form of an LSI together with peripheral circuits fordigital signal processing even when used in the portable telephone orthe like.

A first digital matched filter according to the present invention is adigital matched filter for determining a correlation value between anN-bit digital signal, which is synchronous with a clock, and a digitalcode sequence which includes M digital codes, and comprises:

a) first to M-th digital signal storing means applied with the N-bitdigital signal;

b) digital write selection means for sequentially selecting the first toM-th digital signal storing means one by one in synchronism with theclock to store the N-bit digital signal in the selected digital signalstoring means;

c) a recursive shift register for digital code sequence having first toM-th stages of code flip-flops connected in cascade, and being operativein synchronism with the clock, wherein

the M digital codes are stored in the first to M-th stages of codeflip-flops, respectively, and

an output terminal of the M-th stage of code flip-flop is connected toan input terminal of the first stage of code flip-flop;

d) first to M-th digital multiplication means for multiplying outputsignals of the first to M-th digital signal storing means by outputsignals of the first to M-th stages of code flip-flops, respectively;and

e) digital addition means for adding output signals of the first to M-thdigital multiplication means.

In the M-times spread M-order digital matched filter constructed byusing a FIR digital filter, the digital signal having a large bit numberis not shifted in synchronism with the clock, but the digital code isshifted in synchronism with the clock to determine a correlation valuebetween the two. As a result, the first digital matched filter accordingto the present invention can greatly reduce consumption power duringstorage of the digital signal as compared to the conventional digitalmatched filter in which the digital code is not shifted in synchronismwith the clock but the digital signal having the large bit number isshifted in synchronism with the clock.

A second digital matched filter according to the present invention is adigital matched filter for determining a correlation value between anN-bit digital signal, which is over-sampled by a first clock having afrequency which is m-times as large as a second clock, and a digitalcode sequence which includes M digital codes, and comprises:

a) m×M digital signal storing means applied with the N-bit digitalsignal;

b) digital write selecting means for sequentially selecting the m×Mdigital signal storing means one by one in synchronism with the firstclock to store the N-bit digital signal in the selected digital signalstoring means;

c) first to M-th digital selection means dividing the m×M digital signalstoring means by m to divide the m×M digital signal storing means into Mblocks to sequentially select and output output signals of the m digitalsignal storing means included in the M blocks within one period of thesecond clock;

d) a recursive shift register for digital code sequence having first toM-th stages of code flip-flops which are connected in cascade, and beingoperative in synchronism with the second clock, wherein

the M digital codes are stored in the first to M-th staged of codeflip-flops, respectively, and

an output terminal of the M-th stage of code flip-flop is connected toan input terminal of the first stage of code flip-flop;

e) first to M-th digital multiplication means for multiplying outputsignals of the first to M-th digital selection means by output signalsof the first to M-th stages of code flip-flops, respectively; and

f) digital addition means for adding output signals of the first to M-thdigital multiplication means.

In the M-times spread (m×M)-order digital matched filter constructed byusing an FIR m-times over-sampling interpolation digital filter, thedigital signal having a large bit number is not shifted in synchronismwith the clock, but the digital code is shifted in synchronism with theclock to determine a correlation value between the two. As a result, thesecond digital matched filter according to the present invention cangreatly reduce consumption power during storage of the digital signal ascompared to the conventional digital matched filter in which the digitalcode is not shifted in synchronism with the clock but the digital signalhaving the large bit number is shifted in synchronism with the clock.

A third digital matched filter according to the present invention is adigital matched filter for determining a correlation value between anN-bit digital signal, which is over-sampled by a first clock having afrequency which is m-times as large as a second clock, and a digitalcode sequence which includes M digital codes, and comprises:

a) serial/parallel conversion means for serial/parallel converting thedigital signal serially inputted to output first to m-th digital signalsin parallel;

b) first to m-th digital signal storage means applied with the first tom-th digital signals from the serial/parallel conversion means,respectively, and having each M memory units;

c) digital write selection means for sequentially selecting the M memoryunits one by one in synchronism with the second clock every the first tom-th digital storage means to store the respective first to M-th digitalsignals in the respective selected memory units;

d) first to M-th digital selection means for sequentially selecting andoutputting output signals of the first to m-th digital signal storingmeans within one period of the second clock every the M memory units,respectively;

e) a recursive shift register for digital code sequence having first toM-th stages of code flip-flops which are connected in cascade, and beingoperative in synchronism with the second clock, wherein

the M digital codes are stored in the first to M-th stages of codeflip-flops, respectively, and

an output terminal of the M-th stage of code flip-flop is connected toan input terminal of the first stage of code flip-flop;

f) first to M-th digital multiplication means for multiplying outputsignals of the first to M-th digital selection means by output signalsof the first to M-th stages of code flip-flops, respectively; and

g) digital addition means for adding output signals of the first to M-thdigital multiplication means.

The third digital matched filter according to the present invention usesm M-times spread M-order digital matched filters each constructed byusing a FIR digital filter, and when correlation between the digitalsignal over-sampled by the first clock having a frequency which ism-times the second frequency and the digital code is determined, each ofthe digital signals having a large bit number is not shifted insynchronism with the clock but the digital code is shifted insynchronism with the clock to determine a correlation value between thetwo. As a result, consumption power during storage of the digital signalcan be reduced greatly as compared to the conventional digital matchedfilter in which the digital code is not shifted in synchronism with theclock but each of the digital signals having the large bit number isshifted in synchronism with the clock to determine a correlation valuebetween the two.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing a conventional example of aneight-times spread 8-order digital matched filter constructed by usingan FIR digital filter.

FIG. 2 is a diagram for explaining the procedure for multiplication inthe digital matched filter shown in FIG. 1.

FIG. 3 is a block diagram showing a conventional example of aneight-times spread 16-order digital matched filter constructed by usingan FIR 2-times over-sampling interpolation digital filter.

FIG. 4 is a block diagram showing a digital matched filter according toa first embodiment of the present invention.

FIG. 5 is a diagram for explaining the procedure for multiplication inthe digital matched filter shown in FIG. 4.

FIG. 6 is a block diagram showing a write selection circuit provided ina digital matched filter according to a second embodiment of the presentinvention.

FIG. 7 is a timing chart for explaining the operation of the writeselection circuit shown in FIG. 6.

FIG. 8 is a block diagram showing a digital matched filter according toa third embodiment of the present invention.

FIG. 9 is a block diagram showing a digital matched filter according toa fourth embodiment of the present invention.

FIG. 10 is a block diagram showing a digital matched filter according toa fifth embodiment of the present invention.

BEST MODE FOR CARRYING OUT THE INVENTION

(First Embodiment)

A digital matched filter according to a first embodiment of the presentinvention is an eight-times spread 8-order digital matched filterconstructed by using an FIR digital filter. As shown in FIG. 4, itcomprises a signal input terminal 201, a clock input terminal 202, astorage section 210 including first to eighth flip-flop sets 211-218, awrite selection circuit 220 constructed by using a recursive tappedshift register including first to eighth write selecting flip-flops221-228, a despreading code sequence shift register 230 constructed byusing a recursive tapped shift register including first to eighthdespreading code flip-flops 231-238, first to eighth multipliers241-248, first to seventh adders 251-257, and an output terminal 205.Here, each of the first to eighth flip-flop sets 211-218 constitutingthe storage section 210 is comprised of 6 flip-flops connected inparallel to each other.

A digital signal I_(o) generated by sampling an analog signal (forexample, a spectrum spread signal) at a sampling frequency of 4.096 MHzis inputted to the signal input terminal 201. The digital signal I_(o)is a 6-bit digital signal in terms of two's complement which issynchronous with a clock CLK of 4.096 MHz inputted to the clock inputterminal 202.

Data input terminals D of the first to eighth flip-flop sets 211-218constituting the storage section 210 are applied with the digital signalI_(o). Clock input terminals C of the first to eighth flip-flop sets211-218 are applied with output signals of the first to eighth writeselecting flip-flops 221-228 constituting the write selection circuit220, respectively.

In the initial state, desired one of the first to eighth write selectingflip-flops 221-228 constituting the write selection circuit 220 iswritten with “1” (high level in logical value), and the other writeselecting flip-flops are written with “0”, (low level in logical value).Hereinafter, for simplification of explanation, it is assumed that onlythe eighth write selecting flip-flop 228 is written with “1” in theinitial state. Clock input terminals C of the first to eighth writeselecting flip-flops 221-228 are applied with the clock CLK. When theclock CLK is applied to the clock input terminal C of the eighth writeselecting flip-flop 228, the “1” which has been written to the eighthwrite selecting flip-flop 228 in the initial condition is shifted to thefirst write selecting flip-flop 221. Subsequently, the “1” shifted tothe first write selecting flip-flop 221 is sequentially shifted from thesecond write selecting flip-flop 222 toward the eighth write selectingflip-flop 228 in synchronism with the clock CLK. Thereby, the “1” issequentially applied to the clock input terminals C of the first toeighth flip-flop sets 211-218 constituting the storage section 210 insynchronism with the clock CLK, so that the digital signal I_(o) issequentially fetched and held in the first to eighth flip-flop sets211-218 in synchronism with the clock CLK.

The first to eighth despreading code sequence flip-flops 231-238constituting the despreading code sequence shift register 230 arewritten with despreading codes of an 8-bit despreading code sequence C₇C₆ C₅ C₄ C₃ C₂ C₁ C₀ respectively. Hereinafter, for simplification ofexplanation, it is assumed that in the initial state, the despreadingcodes C₀-C₇ are stored in the first to eighth despreading codeflip-flops 231-238 in order of from the despreading code C₇ to thedespreading code C₀, respectively.

Clock input terminals C of the first to eighth despreading codeflip-flops 231-238 are applied with the clock CLK, and the despreadingcodes C₀-C₇ stored in the first to eighth despreading code flip-flops231-238 are sequentially shifted from the first despreading codeflip-flop 231 toward the eighth despreading code flip-flop 238 insynchronism with the clock CLK. It is to be noted that a despreadingcode which has been shifted to the eighth despreading code flip-flop 238is shifted to the first despreading code flip-flop 231 in synchronismwith the next clock CLK. Thereby, the despreading codes C₀-C₇ areoutputted from the first to eighth despreading code flip-flops 231-238while being sequentially shifted in synchronism with the clock CLK.

Each of the first to eighth multipliers 241-248 is a multiplier for 6bits×1 bit, and outputs an output signal of 6 bits. In the first toeighth multipliers 241-248, multiplication operations of output signals(6 bits) of the first to eighth flip-flop sets 211-218 by thedespreading codes (1 bit) outputted from the first to eighth despreadingcode flip-flops 231-238 are carried out, respectively. For example, inthe multipliers 241-248, when the despreading code indicates “1”,multiplication operations of the output signals of the first to eighthflip-flop sets 211-218 by “1” are carried out. When the despreading codeindicates “0”, multiplication operations of the output signals of thefirst to eighth flip-flop sets 211-218 by “−1”, are carried out.

The procedure for multiplication in the respective multipliers 241-248will be described hereunder with reference to FIG. 5.

In the first operation state, a first sampling data D₀ of the digitalsignal I_(o) is inputted to the signal input terminal 201 in synchronismwith the clock CLK. At the same time, the “1” which has been written inthe eighth write selecting flip-flop 228 of the write selection circuit220 in the initial state is shifted to the first write selectingflip-flop 221 in synchronism with the clock CLK. As a result, the “138is applied to the clock input terminal C of only the first shiftregister set 211 of the storage section 210, and the first sampling dataD₀ is fetched and held in the first shift register set 211. Also, thedespreading code C₀ which has been stored in the eighth despreading codeflip-flop 238 of the despreading code string shift register 230 in theinitial state is shifted to the first despreading code flip-flop 231 insynchronism with the clock CLK. As a result, multiplication of the firstsampling data D₀ by the despreading code C₀ is carried out in the firstmultiplier 241. Accordingly, an output signal indicative of a value ofD₀×C₀ is outputted from the first multiplier 241.

In the second operation state, a second sampling data D₁ of the digitalsignal I_(o) is inputted to the signal input terminal 201 in synchronismwith the clock CLK. At the same time, the “1” which has been shifted tofirst write selecting flip-flop 221 of the write selection circuit 220in the first operation state is shifted to the second write selectingflip-flop 222 in synchronism with the clock CLK. As a result, the “1” isapplied to the clock input terminal C of only the second shift registerset 212 of the storage section 210, and the second sampling data D₁ isfetched and held in the second shift register set 212. At that time, inthe first flip-flop set 211, the first sampling data D₀ which has beenfetched thereto in the first operation state is held as it is. Also, thedespreading codes stored in the despreading code string shift register230 are shifted in synchronism with the clock CLK. As a result, thedespreading code C₀ which has been shifted to the first despreading codeflip-flop 231 in the first operation state is shifted to the seconddespreading code flip-flop 232, and the despreading code C₁ which hasbeen shifted to the eighth despreading code flip-flop 238 in the firstoperation state is shifted to the first despreading code flip-flop 231.Consequently, multiplication of the second sampling data D₁ by thedespreading code C₀ is carried out in the second multiplier 242, andmultiplication of the first sampling data D₀ by the despreading code C₁is carried out in the first multiplier 241. Accordingly, an outputsignal indicative of a value of D₁×C₀ is outputted from the secondmultiplier 242, and an output signal indicative of a value of D₀×C₁ isoutputted from the first multiplier 241.

In the third operation state, a third sampling data D₂ of the digitalsignal I_(o) is inputted to the signal input terminal 201 in synchronismwith the clock CLK. At the same time, the “1” which has been shifted tothe second write selecting flip-flop 222 of the write selection circuit220 in the second operation state is shifted to the third writeselecting flip-flop 223 in synchronism with the clock CLK. As a result,the “1” is applied to the clock input terminal C of only the third shiftregister set 213 of the storage section 210, and the third sampling dataD₂ is fetched and held in the third shift register set 213. At thattime, in the first flip-flop set 211, the first sampling data D₀ whichhas been fetched thereto in the first operation state is held as it is,and in the second flip-flop set 212, the second sampling data D₁ whichhas been fetched thereto in the second operation state is held as it is.Also, the despreading codes stored in the despreading code sequenceshift register 230 are shifted in synchronism with the clock CLK.Consequently, the despreading code C₀ which has been shifted to thesecond despreading code flip-flop 232 in the second operation state isshifted to the third despreading code flip-flop 233, the despreadingcode C₁ which has been shifted to the first despreading code flip-flop231 in the second operation state is shifted to the second despreadingcode flip-flop 232, and the despreading code C₂ which has been shiftedto the eighth despreading code flip-flop 238 in the second operationstate is shifted to the first despreading code flip-flop 231. As aresult, multiplication of the third sampling data D₂ by the despreadingcode C₀ is carried out in the third multiplier 243, multiplication ofthe second sampling data D₁ by the despreading code C₁ is carried out inthe second multiplier 242, and multiplication of the first sampling dataD₀ by the despreading code C₂ is carried out in the first multiplier241. Accordingly, an output signal indicative of a value of D₂×C₀ isoutputted from the third multiplier 243, an output signal indicative ofa value of D₁×C₁ is outputted from the second multiplier 242, and anoutput signal indicative of a value of D₀×C₂ is outputted from the firstmultiplier 241. Subsequently, a similar operation is repeated until theseventh operation state.

In the eighth operation state, an eighth sampling data D₇ of the digitalsignal I_(o) is inputted to the signal input terminal 201 in synchronismwith the clock CLK. At the same time, the “1” which has been shifted tothe seventh write selecting flip-flop 227 of the write selection circuit220 in the seventh operation state is shifted to the eighth writeselecting flip-flop 228 in synchronism with the clock CLK. As a result,the “1” is applied to the clock input terminal C of only the eighthshift register set 218 of the storage section 210, and the eighthsampling data D₇ is fetched and held in the eighth shift register set218. At that time, in the first to seventh flip-flop sets 211-217, thefirst to seventh sampling data D₀-D₆ which have been fetched thereto upto the seventh operation state are held as they are, respectively. Also,the despreading codes stored in the despreading code sequence shiftregister 230 are shifted in synchronism with the clock CLK, so that thedespreading codes C₇-C₀ are stored in the first to eighth despreadingcode flip-flops 231-238, respectively. Thereby, multiplicationoperations of the first to eighth sampling data D₀-D₇ of digital signalI_(o), which are respectively held in the first to eighth flip-flops211-218 of the storage section 210, by the despreading codes C₇-C₀ whichare respectively shifted to the first to eighth despreading codesequence flip-flops 231-238 of the despreading code sequence shiftregister 230 are carried out in the first to eighth multipliers 241-248,respectively. As a result, an output signal indicative of a value ofD₇×C₀ is outputted from the eighth multiplier 248, an output signalindicative of a value of D₆×C₁ is outputted from the seventh multiplier247, an output signal indicative of a value of D₅×C₂ is outputted fromthe sixth multiplier 246, an output signal indicative of a value ofD₄×C₃ is outputted from the fifth multiplier 245, an output signalindicative of a value of D₃×C₄ is outputted from the fourth multiplier244, an output signal indicative of a value of D₂×C₅ is outputted fromthe third multiplier 243, an output signal indicative of a value ofD₁×C₆ is outputted from the second multiplier 242, and an output signalindicative of a value of D₀×C₇ is outputted from the first multiplier241.

Through the above operation, multiplication operations necessary todetermine a correlation value between the initial 8-sampling data D₇ D₆D₅ D₄ D₃ D₂ D₁ D₀ of the digital signal I_(o) and the 8-bit despreadingcode sequence C₇ C₆ C₅ C₄ C₃ C₂ C₁ C. are all carried out.

In the ninth operation state, a ninth sampling data D₈ of the digitalsignal I_(o) is inputted to the signal input terminal 201 in synchronismwith the clock CLK. At the same time, the “1” which has been shifted tothe eighth write selecting flip-flop 228 of the write selection circuit220 in the eighth operation state is shifted to the first writeselecting flip-flop 221 in synchronism with the clock CLK. As a result,the “1” is applied to the clock input terminal C of only the first shiftregister set 211 of the storage section 210, and the ninth sampling dataD₈ is fetched and held in the first shift register set 211. At thattime, in the second to eighth flip-flop sets 211-218, the second toeighth sampling data D₁-D₇ which have been fetched thereto up to theeighth operation state are held as they are, respectively. Also, thedespreading codes stored in the despreading code sequence shift register230 are shifted in synchronism with the clock CLK. Consequently, thedespreading code C₀ is stored in the first despreading code flip-flop231, and the despreading codes C₇-C₁ are stored in the second to eighthdespreading code flip-flops 232-238, respectively. Thereby,multiplication of the ninth sampling data D₈ of the digital signal I_(o)held in the first flip-flop 211 of the storage section 210 by thedespreading code C₀ stored in the first despreading code flip-flop 231of the despreading code sequence shift register 230 is carried out inthe first multiplier 241, and multiplication operations of the second toeighth sampling data pieces D₁-D₇ of the digital signal I_(o), which arerespectively held in the second to ninth flip-flops 212-218, by thedespreading codes C₇-C₁ which are respectively stored in the second toeighth despreading code flip-flops 231-238 of the despreading codesequence shift register 230 are carried out in the second to eighthmultipliers 242-248, respectively. As a result, an output signalindicative of a value of D₈×C₀ is outputted from the first multiplier241, an output signal indicative of a value of D₇×C₁ is outputted fromthe eighth multiplier 248, an output signal indicative of a value ofD₆×C₂ is outputted from the seventh multiplier 247, an output signalindicative of a value of D₅×C₃ is outputted from the sixth multiplier246, an output signal indicative of a value of D₄×C₄ is outputted fromthe fifth multiplier 245, an output signal indicative of a value ofD₃×C₅ is outputted from the fourth multiplier 244, an output signalindicative of a value of D₂×C₆ is outputted from the third multiplier243, and an output signal indicative of a value of D₁×C₇ is outputtedfrom the second multiplier 242.

Consequently, multiplication operations necessary to determine acorrelation value between the 8-sampling data D₈ D₇ D₆ D₅ D₄ D₃ D₂ D₁ ofdigital signal I_(o) which is one sampling after the initial 8-samplingdata D₇ D₆ D₅ D₄ D₃ D₂ D₁ D₀ and the 8-bit despreading code string C₇ C₆C₅ C₄ C₃ C₂ C₁ C₀ are all carried out. Subsequently, a similar operationis repeated.

Each of the first to fourth adders 251-254 is an adder for 6 bits+6bits, and outputs an output signal of 7 bits. Each of the fifth andsixth adders 255 and 256 is an adder for 7 bits+7 bits, and outputs anoutput signal of 8 bits. The seventh adder 257 is an adder for 8 bits +8bits, and outputs an output signal of 9 bits. In the first adder 251,addition of the output signal (6 bits) of the first multiplier 241 andthe output signal (6 bits) of the second multiplier 242 is carried out.In the second adder 252, addition of the output signal (6 bits) of thethird multiplier 243 and the output signal (6 bits) of the fourthmultiplier 244 is carried out. In the third adder 253, addition of theoutput signal (6 bits) of the fifth multiplier 255 and the output signal(6 bits) of the sixth multiplier 256 is carried out. In the fourth adder254, addition of the output signal (6 bits) of the seventh multiplier247 and the output signal (6 bits) of the eighth multiplier 248 iscarried out. In the fifth adder 255, addition of the output signal (7bits) of the first adder 251 and the output signal (7 bits) of thesecond adder 252 is carried out. In the sixth adder 256, addition of theoutput signal (7 bits) of the third adder 253 and the output signal (7bits) of the fourth adder 254 is carried out. In the seventh adder 257,addition of the output signal (8 bits) of the fifth adder 255 and theoutput signal (8 bits) of the sixth adder 256 is carried out. As aresult, a correlation value MFOUT between the digital signal I_(o) andthe despreading code sequence C₇ C₆ C₅ C₄ C₃ C₂ C₁ C₀ is obtained in theseventh adder 257, and is outputted to the outside through the outputterminal 205.

Next, comparison of consumption power in the digital matched filteraccording to the present embodiment with that in the conventionaldigital matched filter shown in FIG. 1 will be described. In the digitalmatched filter according to the present embodiment, write of the digitalsignal I_(o) to the storage section 210 at each clock CLK is carried outat only one of the first to eighth flip-flop sets 211-218. Accordingly,on the assumption that consumption power in one flip-flop constitutingthe respective flip-flop sets 211-218 is W, consumption power in thestorage section 210 is 6 W. Also, in the digital matched filteraccording to the present embodiment, the first to eighth write selectingflip-flops 221-228 constituting the write selection circuit 220 and thefirst to eighth despreading code flip-flops 231-238 constituting thedespreading code sequence shift register 230 operate in synchronism withthe clock CLK. Hence, consumption power in the write selection circuit220 and despreading code sequence shift register 230 is 2×8 W=16 W.Accordingly, consumption power in the storage section 210, writeselection circuit 220 and despreading code sequence shift register 230of the digital matched filter according to the present embodimentamounts up to 6 W+16 W=22 W. Contrary to this, in the conventionaldigital matched filter shown in FIG. 1, all of the first to seventhflip-flop sets 11-18 are operated in synchronism with the clock CLK whenthe digital signal I_(o) is written to the tapped shift register 10 ateach clock CLK. Hence, consumption power in the tapped shift register 10is 6×7 W=42 W. Accordingly, as consumption power in the first to eighthmultipliers 241-248 and first to seventh adders 251-257 of the digitalmatched filter according to the present embodiment is identical to thatin the first to eighth multipliers 21-28 and first to seventh adders31-37 of the conventional digital matched filter shown in FIG. 1, theconsumption power in the digital matched filter according to the presentembodiment is 22 W/42 W≈1/2 as compared to the consumption power in theconventional digital matched filter shown in FIG. 1.

Generally, given that the number of bits of the digital signal I_(o) isN in an M-times spread M-order digital matched filter, each of theflip-flop sets of the storage section 210 includes N flip-flops, andeach of the write selection circuit 220 and despreading code sequenceshift register 230 includes M flip-flops in the digital matched filteraccording to the present embodiment. Accordingly, consumption power inthe storage section 210, write selection circuit 220 and despreadingcode sequence shift register 230 of the digital matched filter accordingto the present embodiment is NW+MW+MW=(N+M+M)W. Contrary to this, in theconventional digital matched filter shown in FIG. 1, the tapped shiftregister 10 includes (M−1)N flip-flops, so that consumption power in thetapped shift register 10 is (M−1)NW. Accordingly, the consumption powerin the digital matched filter according to the present embodiment is(N+M+M)W/(M−1)NW=(N+M+M)/(M−1)N as compared to the consumption power inthe conventional digital matched filter shown in FIG. 1. As M>>1 isgenerally satisfied, the consumption power in the digital matched filteraccording to the present embodiment is 1/M+1/N+1/N as compared to theconsumption power in the conventional digital matched filter shown inFIG. 1.

In the foregoing description, each despreading code constituting thedespreading code sequence C₇ C₆ C₅ C₄ C₃ C₂ C₁ C₀ is of 1 bit. However,the number of bits of each despreading code constituting the despreadingcode sequence of C₇ C₆ CS C₄ C₃ C₂ C₁ C₀ may sometimes be two or more(provided that the bit number of each despreading code is smaller thanthat of the digital signal I_(o)). For example, each despreading codemay be of 2 bits to indicate 1, 0, −1. When the bit number of eachdespreading code is two or more, a despreading code sequence shiftregister constructed of a recursive tapped shift register using 8flip-flop sets each including two or more flip-flops connected inparallel to each other may be used in place of the despreading codesequence shift register 230 shown in FIG. 4.

Each of the first to eighth multipliers 241-248 may not necessarily be amultiplier constructed of a logical circuit, and may be means foroutputting the same multiplication result (for example, a circuit whichoutputs an input signal as it is when the despreading code is “1”, andwhich inverts the code bit of the input signal and outputs a resultingsignal when the despreading code is “0” (multiplication of coefficient“−1”)).

(Second Embodiment)

A digital matched filter according to a second embodiment of the presentinvention differs from the previously-described digital matched filteraccording to the first embodiment in that it comprises a write selectioncircuit 300 shown in FIG. 6 in place of the write selection circuit 220shown in FIG. 4.

As shown in FIG. 6, the write selection circuit 300 provided in thedigital matched filter according to the present embodiment isconstructed by using a recursive tapped shift register including firstto eighth write selecting flip-flops 311-318 and a selector circuit 320.Clock input terminals C of the first to eighth write selectingflip-flops 311-318 are applied with a clock CLK of 4.096 MHz through aclock input terminal 301. Reset terminals R of the first to eighth writeselecting flip-flops 311-318 are applied with a reset signal RS througha reset signal input terminal 302. A first input terminal A of theselector circuit 320 is applied with an output signal Q₈ of the eighthwrite selecting flip-flop 318. A second input terminal B of the selectorcircuit 320 is applied with power supply voltage Vcc (voltagecorresponding to high level in logical value). A selection terminal S ofthe selection circuit 320 is applied with a write timing control signalWE through a timing control signal input terminal 303. An outputterminal Y of the selector circuit 320 is connected to a data inputterminal D of the first write selecting flip-flop 311. It is to be notedthat in the selector circuit 320, the second input terminal B isselected when the write timing control signal WE is “1” (high level inlogical value), and the first input terminal A is selected when thewrite timing control signal WE is “0” (low level in logical value).

Next, operation of the write selection circuit 300 will be describedwith reference to a timing chart shown in FIG. 7. At time preceding timet₀, the reset signal RS is “0”, so that the first to eighth writeselecting flip-flops 311-318 are all reset and output signals Q₁-Q₈ ofthe first to eighth write selecting flip-flops 311-318 are all renderedto be “0”. When the write timing control signal WE is rendered to be “1”at time t₁ after the reset signal RS is rendered to be “1” at time t₀,the second input terminal B is selected in the selector circuit 320, andthe output signal outputted from the output terminal Y of the selectorcircuit 320 is rendered to be “1”. As a result, with the clock CLKchanged from “0” to “1” at time t₂, the output signal of the selectorcircuit 320 is fetched and held in the first write selecting flip-flop311, rendering output signal Q₁ of the first write selecting flip-flop311 to be “1”. At that time, output signals Q₁-Q₇ (all zero) of first toseventh write selecting flip-flops 311-317 at time t, are fetched andheld in the second to eighth write selecting flip-flops 312-318,respectively, so that output signals Q₂-Q₈ of the second to eighth writeselecting flip-flops 312-318 remain to be “0”.

When the write timing control signal WE is rendered to be “0” at timet₃, the first input terminal A is selected in the selector circuit 320and the output signal Q₈ of the eighth write selecting flip-flop 318 isoutputted from the output terminal Y of the selector circuit 320. As aresult, with the clock CLK changed from “0” to “1” at time t₄, theoutput signal Q. of the eighth write selecting flip-flop 318 is fetchedand held in the first write selecting flip-flop 311, rendering theoutput signal Q₁ of the first write selecting flip-flop 311 to be “0”.The output signal Q₁ of the first write selecting flip-flop 311 at timet₃ is fetched and held in the second write selecting flip-flop 312, sothat the output signal Q₂ of the second write selecting flip-flop 312 isrendered to be “1”. The output signals Q₂-Q₇ of the second to seventhwrite selecting flip-flops 312-317 at time t₃ are fetched and held inthe third to eighth write selecting flip-flops 313-318, respectively, sothat the output signals Q₃-Q₈ of the third to eighth write selectingflip-flops 313-318 remain to be “0”. Subsequently, a similar operationis repeated. Consequently, as shown in FIG. 6, the “1” fetched and heldin the first write selecting flip-flop 311 at time t2 is shifted fromthe first write selecting flip-flop 311 to the eighth write selectingflip-flop 318 in synchronism with the clock CLK. Further, the “1”fetched and held in the eighth write selecting flip-flop 318 is shiftedto the first write selecting flip-flop 311 in synchronism with the clockCLK.

Consumption power in the digital matched filter according to the presentembodiment can be reduced as compared to consumption power in theconventional digital matched filter shown in FIG. 1. Because onlyconsumption power in the selector circuit 320 is added to theconsumption power in the previously-described digital matched filteraccording to the first embodiment.

(Third Embodiment)

A digital matched filter according to a third embodiment of the presentinvention is an eight-times spread 16-order digital matched filterconstructed by using an FIR 2-times over-sampling interpolation digitalfilter. As shown in FIG. 8, it comprises a signal input terminal 401, afirst clock input terminal 402, a second clock input terminal 403, astorage section 410 including first to sixteenth flip-flop sets 411-426,a write selection circuit 430 constructed by using a recursive tappedshift register including first to sixteenth write selecting flip-flops431-446, first to eighth selector circuit sets 451-458, a despreadingcode sequence shift register 460 constructed by using a recursive tappedshift register including first to eighth despreading code flip-flops461-468, first to eighth multipliers 471-478, first to seventh adders481-487, and an output terminal 405. Here, each of the first tosixteenth flip-flop sets 411-426 constituting the storage section 410includes 6 flip-flops connected in parallel to each other. Also, each ofthe first to eighth selector circuit sets 451-458 includes 6 selectorcircuits connected in parallel to each other.

A digital signal I_(o) generated by doubly over-sampling an analogsignal (spectrum spread signal) at a sampling frequency of 8.192 MHz isinputted to the signal input terminal 401. The digital signal I_(o) is a6-bit digital signal in terms of two's complement which is synchronouswith a first clock CLK1 of 8.192 MHz inputted to the first clock inputterminal 402. Data input terminals D of the first to sixteenth flip-flopsets 411-426 constituting the storage section 410 are applied with thedigital signal I_(o). Clock input terminals C of the first to sixteenthflip-flop sets 411-426 are applied with output signals of the first tosixteenth write selecting flip-flops 431-446 constituting the writeselection circuit 430, respectively.

In the initial state, desired one of the first to sixteenth writeselecting flip-flops 431-446 constituting the write selection circuit430 is written with “1”, and the other write selecting flip-flops arewritten with “0”. Hereinafter, for simplification of explanation, it isassumed that in the initial state, the “1” is written and held in onlythe sixteenth write selecting flip-flop 446. Clock input terminals C ofthe first to sixteenth write selecting flip-flops 431-446 are appliedwith the first clock CLK1. With the first clock CLK1 applied to theclock input terminal C of the sixteenth write selecting flip-flop 446,the “1” held in the sixteenth write selecting flip-flop 446 is shiftedto the first write selecting flip-flop 431. Subsequently, the “1”shifted to the first write selecting flip-flop 431 is shifted from thesecond write selecting flip-flop 432 toward the sixteenth writeselecting flip-flop 446 in synchronism with the first clock CLK1.Thereby, the “1” is sequentially applied to the clock input terminals Cof the first to sixteenth flip-flop sets 411-426 constituting thestorage section 410 in synchronism with the first clock CLK1. Hence, thedigital signal I_(o) is sequentially fetched and held in the first tosixteenth flip-flop sets 411-426 in synchronism with the first clockCLK1.

A second clock CLK2 of 4.096 MHz is inputted to the second clock inputterminal 403. Selection terminals S of the respective selector circuitsconstituting each of the first to eighth selector circuit sets 451-458are applied with the second clock CLK2. When the second clock CLK2 is“1”, a first input terminal A is selected. When the second clock CLK2 is“0”, a second input terminal B is selected. Accordingly, when the secondclock CLK2 is “1”, output signals of the odd flip-flop sets 411, 413,415, 417, 419, 421, 423 and 425 of storage section 410 which areconnected to the first input terminals A of the first to eighth selectorcircuit sets 451-458 are outputted from output terminals Y of the firstto eighth selector circuit sets 451-458, respectively. On the otherhand, when the second clock CLK2 is “0”, output signals of the evenflip-flop sets 412, 414, 416, 418, 420, 422, 424 and 426 of storagesection 410 which are connected to the second input terminals B of thefirst to eighth selector circuit sets 451-458 are outputted from theoutput terminals Y of the first to eighth selector circuit sets 451-458,respectively.

The first to eighth despreading code flip-flops 461-468 constituting thedespreading code sequence shift register 460 are written with thedespreading codes of an 8-bit despreading code sequence C₇ C₆ C₅ C₄ C₃C₂ C₁ C₀, respectively. Hereinafter, for simplification of explanation,it is assumed that in the initial state, the despreading codes C₀-C₇ arestored in the first to eighth despreading code flip-flops 461-468 inorder of from the despreading code C₇ to the despreading code C₀,respectively. Clock input terminals C of the first to eighth despreadingcode flip-flops 461-468 are applied with the second clock CLK2 of 4.096MHz which is synchronous with the first clock CLK1 of 8.192 MHz, and thedespreading codes stored in the first to eighth despreading codeflip-flops 461-468 are shifted from the first despreading code flip-flop461 toward the eighth despreading code flip-flop 468 in synchronism withthe second clock CLK2. It is to be noted that a despreading code whichhas been shifted to the eighth despreading code flip-flop 468 is shiftedto the first despreading code flip-flop 461 in synchronism with the nextsecond clock CLK2. Thereby, the despreading codes C₀-C₇ are sequentiallyshifted in synchronism with the second clock CLK2, and outputted fromthe first to eighth despreading code flip-flops 461-468.

Each of the first to eighth multipliers 471-478 is a multiplier for 6bits×1 bits, and outputs an output signal of 6 bits. In the first toeighth multipliers 471-478, multiplication operations of the outputsignals (6 bits) of the first to eighth selector circuit sets 451-458 bythe despreading codes (1 bit) outputted from the first to eighthdespreading code flip-flops 461-468 are carried out. In the multipliers471-478, for example, when the despreading code indicates “1”,multiplication operations of the output signals of the first to eighthselector circuit sets 451-458 by “1” are carried out. When thedespreading code indicates “0”, multiplication operations of the outputsignals of the first to eighth selector circuit sets 451-458 by “−1”,are carried out.

Each of the first to fourth adders 481-484 is an adder for 6 bits+6bits, and outputs an output signal of 7 bits. Each of the fifth andsixth adders 485 and 486 is an adder for 7 bits+7 bits, and outputs anoutput signal of 8 bits. The seventh adder 487 is an adder for 8 bits+8bits, and outputs an output signal of 9 bits. In the first adder 481,addition of the output signal (6 bits) of the first multiplier 471 andthe output signal (6 bits) of the second multiplier 472 is carried out.In the second adder 482, addition of the output signal (6 bits) of thethird multiplier 473 and the output signal (6 bits) of the fourthmultiplier 474 is carried out. In the third adder 483, the output signal(6 bits) of the fifth multiplier 475 and the output signal (6 bits) ofthe sixth multiplier 476 is carried out. In the fourth adder 484,addition of the output signal (6 bits) of the seventh multiplier 477 andthe output signal (6 bits) of the eighth multiplier 478 is carried out.In the fifth adder 485, addition of the output signal (7 bits) of thefirst adder 481 and the output signal (7 bits) of the second adder 482is carried out. In the sixth adder 486, addition of the output signal (7bits) of the third adder 483 and the output signal (7 bits) of thefourth adder 484 is carried out. In the seventh adder 487, addition ofthe output signal (8 bits) of the fifth adder 485 and the output signal(8 bits) of the sixth adder 486 is carried out.

In the digital matched filter according to the present embodimentconstructed as above, when 16 first clocks CLK1 are inputted followingthe initial state, the initial first to sixteenth sampling data D₀-D₁₅of the digital signal I_(o) are written and held in the first tosixteenth flip-flop sets 411-426 constituting the storage section 410,respectively. At the same time, the despreading codes C₇-C₀ are shiftedto the first to eighth flip-flops 461-468 constituting the despreadingcode sequence shift register 460 and held therein, respectively. As aresult, when the second clock CLK2 is “1”, the odd sampling data D₀, D₂,D₄, D₆, D₈, D₁₀, D₁₂ and D₁₄ of the digital signal I_(o) are selected bymeans of the first to eighth selector circuit sets 451-458, so that D₁₄(C₀+D₁₂×C₁+D₁₀×C₂+D₈×C₃+D₆×C₄+D₄×C₅+D₂×C₆+D₀×C₇ is obtained in theseventh adder 487. Consequently, a correlation value MFOUT between theodd sampling data pieces D₀, D₂, D₄, D₆, D₈, D₁₀, D₁₂ and D₁₄ of theinitial 16 sampling data D₀-D₁₅ of the digital signal I_(o) and the8-bit despreading code sequence C₇ C₆ C₅ C₄ C₃ C₂ C₁ C₀ is obtained andoutputted to the outside through the output terminal 405. When thesecond clock CLK2 is “0”, the even sampling data D₁, D₃, D₅, D₇, D₉,D₁₁, D₁₃ and D₁₅ of the digital signal I_(o) are selected by means ofthe first to eighth selector circuit sets 451-458, so that D₁₅(C₀+D₁₃×C₁+D₁₁×C₂+D₉×C₃+D₇×C₄+D₅×C₅+D₃×C₆+D₁×C₇ is obtained in theseventh adder 487. Consequently, a correlation value between the evensampling data D₁, D₃, D₅, D₇, D₉, D₁₁, D₁₃ and D₁₅ of the initial 16sampling data D₀-D₁₅ of the digital signal I_(o) and the 8-bitdespreading code sequence C₇ C₆ C₅ C₄ C₃ C₂ C₁ C₀ is obtained andoutputted to the outside through the output terminal 405.

Next, comparison of consumption power in the digital matched filteraccording to the present embodiment with that in the conventionaldigital matched filter shown in FIG. 3 will be described. In the digitalmatched filter according to the present embodiment, during write of thedigital signal I_(o), the first to sixteenth flip-flop sets 411-426constituting the storage section 410 are operated only one by one insynchronism with the first clock CLK1. Accordingly, on the assumptionthat consumption power in one flip-flop is W, consumption power in thestorage section 410 is identical to the total consumption power in the 6flip-flops constituting each flip-flop set, amounting up to 6 W. Thefirst to sixteenth write selecting flip-flops 431 to 446 constitutingthe write selection circuit 430 are operated each time that the firstclock CLK1 is inputted, so that consumption power in the write selectioncircuit 430 is 16 W. The first to eighth despreading code flip-flops461-468 constituting the despreading code sequence shift register 460are operated in synchronism with the second clock CLK2 having afrequency which is ½ of that of the first clock CLK1, so thatconsumption power in the despreading code sequence shift register 460 is8 W/2=4 W. Accordingly, consumption power in the storage section 410,write selection circuit 430 and despreading code sequence shift register460 of the digital matched filter according to the present embodiment is6 W+16 W+4 W=26 W. Contrary to this, in the conventional digital matchedfilter shown in FIG. 3, the first to fourteenth flip-flop sets 111-124constituting the tapped shift register 110 are operated each time thatthe clock CLK is inputted, so that consumption power in the tapped shiftregister 110 is 6×14 W=84 W. Consumption power in the first to eighthmultipliers 471-478 and first to seventh adders 481-487 of the digitalmatched filter according to the present embodiment is identical toconsumption power in the first to eighth multipliers 131-138 and firstto seventh adders 141-147 of the conventional digital matched filtershown in FIG. 3. Accordingly, when consumption power in the first toeighth selector circuit sets 451-458 of the digital matched filteraccording to the present embodiment is neglected because it is small,consumption power in the digital matched filter according to the presentembodiment is 26 W/84 W≈1/3 as compared to consumption power in theconventional digital matched filter shown in FIG. 3. Generally, giventhat the number of bits of the digital signal I_(o) is N in an M-orderdigital matched filter of FIR m-times over-sampling interpolation filterstructure, the storage section 410 includes MN flip-flops, the writeselection circuit 430 includes M write selecting flip-flops and thedespreading code sequence shift register 460 includes M/m despreadingcode flip-flops in the digital matched filter according to the presentembodiment. However, the flip-flop sets constituting the storage section410 are operated only one by one in synchronism with the first clockCLK1. Further, the spreading code sequence shift register 460 isoperated in synchronism with the second clock CLK2 having a frequencywhich is 1/m of that of the first clock CLK1. Therefore, consumptionpower in the storage section 410, write selection circuit 430 anddespreading code sequence shift register 460 of the digital matchedfilter according to the present embodiment is NW+MW+(M/m²)W=(N+M+M/m²)W.Contrary to this, in the digital matched filter shown in FIG. 3, thetapped shift register 110 includes (M−1)N flip-flops. Therefore,consumption power in the tapped shift register 110 is (M−1)NW.Accordingly, consumption power in the digital matched filter accordingto the present embodiment is (N+M+M/m²)W/(M−1)NW=(N+M+M/m²)/(M−1)N ascompared to consumption power in the conventional matched filter shownin FIG. 3. As M>>1 is generally satisfied, the consumption power in thedigital matched filter according to the present embodiment is1/M+1N+1/m²N as compared to the consumption power in the conventionaldigital matched filter shown in FIG. 3.

In the digital matched filter according to the present embodiment, awrite selection circuit constructed by using a recursive tapped shiftregister which includes the first to sixteenth write selectingflip-flops and the selector circuit as the write selection circuit 300shown in FIG. 6 may be used in place of the write selection circuit 430.

In the foregoing description, each despreading code constituting thedespreading code sequence C₇ C₆ C₅ C₄ C₃ C₂ C₁ C₀ is of 1 bit. However,the bit number of each despreading code constituting the despreadingcode sequence C₇ C₆ C₅ C₄ C₃ C₂ C₁ C₀ may sometimes be two or more(provided that the bit number of each despreading code is smaller thanthat of the digital signal I_(o)). For example, each despreading codemay be of 2 bits to indicate 1, 0, −1. When the bit number of eachdespreading code is two or more, a despreading code sequence shiftregister constructed of a recursive tapped shift register by using 8flip-flop sets each including two or more flip-flops connected inparallel to each other may be used in place of the despreading codesequence shift register 460 shown in FIG. 8.

Each of the first to eighth multipliers 471-478 may not necessarily be amultiplier constructed of a logical circuit, and may be means foroutputting the same multiplication result (for example, a circuit whichoutputs an input signal as it is when the despreading code is “1”, andwhich inverts the code bit of an input signal and outputs a resultingsignal when the despreading code is “0”, (multiplication of coefficient“−1”)).

(Fourth Embodiment)

A digital matched filter according to a fourth embodiment of the presentinvention is a digital matched filter for a case where a digital signalI_(o) over-sampled at 8.192 MHz is inputted serially in synchronism witha clock of 8.192 MHz. As shown in FIG. 9, it comprises a signal inputterminal 501, a clock input terminal 502, a serial/parallel converter590, an inverter 595, a first storage section 510 including first toeighth flip-flop sets 511-518, a first write selection circuit 520constructed by using a recursive tapped shift register including firstto eighth write selecting flip-flops 521-528, a second storage section530 including ninth to sixteenth flip-flop sets 531-538, a second writeselection circuit 540 constructed by using a recursive tapped shiftregister including ninth to sixteenth write selecting flip-flops541-548, first to eighth selector circuit sets 551-558, a despreadingcode sequence shift register 560 constructed by using a recursive tappedshift register including first to eighth despreading code flip-flops561-568, first to eighth multipliers 571-578, first to seventh adders581-587, and an output terminal 505. Here, each of the first to eighthflip-flop sets 511-518 constituting the first storage section 510 andeach of the ninth to sixteenth flip-flop sets 531-538 constituting thesecond storage section 530 are each comprised of 6 flip-flops connectedin parallel to each other. Also, each of the first to eighth selectorcircuit sets 551-558 includes 6 selector circuits connected in parallelto each other.

A digital signal I_(o) of 8.192 MHz period generated by over-sampling ananalog signal (spectrum spread signal) at a sampling frequency of 8.192MHz is inputted to the signal input terminal 501. The digital signalI_(o) is a 6-bit digital signal in terms of two's complement. Thedigital signal I_(o) is subjected to the serial/parallel conversion bymeans of the serial/parallel converter 590 so as to be separated into afirst digital signal I₀₁ consisting of odd sampling data and a seconddigital signal I₀₂ consisting of even sampling data. The first digitalsignal I₀₁ is outputted to the first storage section 510 from a firstoutput terminal A of the serial/parallel converter 590. The seconddigital signal I₀₂ is outputted to the second storage section 530 from asecond output terminal B of the serial/parallel converter 590.

Data input terminals D of the first to eighth flip-flop sets 511-518constituting the first storage section 510 are connected to the firstoutput terminal A of the serial/parallel converter 502. Clock inputterminals C of the first to eighth flip-flop sets 511-518 are appliedwith output signals of the first to eighth write selecting flip-flops521-528 constituting the first write selection circuit 520,respectively. In the initial state, “1” is written and held in desiredone of the first to eighth write selecting flip-flops 521-528, and “0”is written and held in the other write selecting flip-flops.Hereinafter, for simplification of explanation, it is assumed that inthe initial state, the “1” is written and held in only the eighth writeselecting flip-flop 528. Clock input terminals C of the first to eighthwrite selecting flip-flops 521-528 are applied with a clock CLK. Whenthe clock CLK is applied to the clock input terminal C of the eighthwrite selecting flip-flop 528, the “1” which has been held in the eighthwrite selecting flip-flop 528 is shifted to the first write selectingflip-flop 521. Subsequently, the ”. shifted to the first write selectingflip-flop 521 is shifted from the second write selecting flip-flop 521toward the eighth write selecting flip-flop 528 in synchronism with theclock CLK. Thereby, the “1” is sequentially applied to the clock inputterminals C of the first to eighth flip-flop sets 511-518 constitutingthe first storage section 510 in synchronism with the clock CLK. As aresult, the first digital signal I₀₁ is sequentially fetched and held inthe first to eighth flip-flop sets 511-518 in synchronism with the clockCLK.

Data input terminals D of the ninth to sixteenth flip-flop sets 531-538constituting the second storage section 530 are connected to the secondoutput terminal B of the serial/parallel converter 590. Clock inputterminals C of the ninth to sixteenth flip-flop sets 531-538 are appliedwith output signals of the first to eighth write selecting flip-flops541-548 constituting the second write selection circuit 540,respectively. In the initial state, “1” is written and held in desiredone of the ninth to sixteenth write selecting flip-flops 541-548, and“0” is written and held in the other write selecting flip-flops.Hereinafter, for simplification of explanation, it is assumed that inthe initial state, the “1” is written and held in only the sixteenthwrite selecting flip-flop 548. Clock input terminals C of the ninth tosixteenth write selecting flip-flops 541-548 are applied with a clock(hereinafter called “inverted clock CLKB”) obtained by inverting thepolarity of the clock CLK by means of the inverter 595. When theinverted clock CLKB is applied to the clock input terminal C of thesixteenth write selecting flip-flop 548, the “1” which has been held inthe sixteenth write selecting flip-flop 548 is shifted to the ninthwrite selecting flip-flop 541. The “1” shifted to the ninth writeselecting flip-flop 541 is subsequently shifted from the ninth writeselecting flip-flop 541 to the sixteenth write selecting flip-flop 548in synchronism with the inverted clock CLKB. Thereby, the “1” issequentially applied to the clock input terminals C of the eighth tosixteenth flip-flop sets 531-538 constituting the second storage section530 in synchronism with the inverted clock CLKB. As a result, the seconddigital signal I₀₂ is sequentially fetched and held in the ninth tosixteenth flip-flop sets 531-538 in synchronism with the inverted clockCLKB.

Selection terminals S of the respective selector circuits constitutingthe first to eighth selector circuit sets 551-558 are applied with theclock CLK. When the clock CLK is “1”, a first input terminal A isselected, and when the clock CLK is “0”, a second input terminal B isselected. Accordingly, when the clock CLK is “1”, output signals of thefirst to eighth flip-flop sets 511-518 constituting the first storagesection 510 which are connected to the first input terminals A of thefirst to eighth selector circuit sets 551-558 are selected and outputtedfrom output terminals Y of the first to eighth selector circuit sets551-558, respectively. On the other hand, when the clock CLK is “0”,output signals of the ninth to sixteenth flip-flop sets 531-538constituting the second storage section 530 which are connected to thesecond input terminals B of the first to eighth selector circuit sets551-558 are selected and outputted from the output terminals Y of thefirst to eighth selector circuit sets 551-558, respectively.

The first to eighth despreading code flip-flops 561-568 constituting thedespreading code sequence shift register 560 are stored with despreadingcodes of an 8-bit despreading code sequence C₇ C₆ C₅ C₄ C₃ C₂ C₁ C₀,respectively. Hereinafter, for simplification of explanation, it isassumed that in the initial state, the despreading codes C₇-C₀ arestored in the first to eighth despreading code flip-flops 561-568,respectively. Clock input terminals C of the first to eighth despreadingcode flip-flops 561-568 are applied with the clock CLK. The despreadingcodes stored in the first to eighth despreading code flip-flops 561-568are shifted from the first despreading code flip-flop 561 toward theeighth despreading code flip-flop 568 in synchronism with the clock CLK.It is to be noted that a despreading code which has been shifted to theeighth despreading code flip-flop 568 is shifted to the firstdespreading code flip-flop 561 in synchronism with the next clock CLK.Thereby, the despreading codes C₀-C₇ are sequentially shifted andoutputted from the first to eighth despreading code flip-flops 561-568in order of from the despreading code C₀ to the despreading code C₇ thein synchronism with the clock CLK.

Each of the first to eighth multipliers 571-578 is a multiplier for 6bits×1 bit, and outputs an output signal of 6 bits. In the first toeighth multipliers 571-578, multiplication operations of the firstdigital signal I₀₁ (6 bits) outputted from the first to eighth selectorcircuit sets 551-558 by the despreading codes (1 bit) outputted from thefirst to eighth despreading code flip-flops 561-568 are respectivelycarried out during the period in which the clock CLK is “1”. At the sametime, multiplication operations of the second digital signal I₀₂ (6bits) outputted from the first to eighth selector circuit sets 551-558by the despreading codes (1 bit) outputted from the first to eighthdespreading code flip-flops 561-568 are respectively carried out duringthe period in which the clock CLK is “0”. For example, when thedespreading code indicates “1”, multiplication operations of the outputsignals of the first to eighth selector circuit sets 551-558 by “1” arecarried out in the multipliers 571-578. When the despreading codeindicates “0”, multiplication operations of the output signals of thefirst to eighth selector circuit sets 551-558 by “−1” are carried out.

Each of the first to fourth adders 581-584 is an adder for 6 bits+6bits, and outputs an output signal of 7 bits. Each of the fifth andsixth adders 585 and 586 is an adder for 7 bits+7 bits, and outputs anoutput signal of 8 bits. The seventh adder 587 is an adder for 8 bits+8bits, and outputs an output signal of 9 bits. In the first adder 581,addition of the output signal (6 bits) of the first multiplier 571 andthe output signal (6 bits) of the second multiplier 572 is carried out.In the second adder 582, addition of the output signal (6 bits) of thethird multiplier 573 and the output signal (6 bits) of the fourthmultiplier 574 is carried out. In the third adder 583, addition of theoutput signal (6 bits) of the fifth multiplier 575 and the output signal(6 bits) of the sixth multiplier 576 is carried out. In the fourth adder584, addition of the output signal (6 bits) of the seventh multiplier577 and the output signal (6 bits) of the eighth multiplier 578 iscarried out. In the fifth adder 585, addition of the output signal (7bits) of the first adder 581 and the output signal (7 bits) of thesecond adder 582 is carried out. In the sixth adder 586, addition of theoutput signal (7 bits) of the third adder 583 and the output signal (7bits) of the fourth adder 584 is carried out. In the seventh adder 587,addition of the output signal (8 bits) of the fifth adder 585 and theoutput signal (8 bits) of the sixth adder 586 is carried out.

In the digital matched filter according to the present embodimentconstructed as above, when 16 clocks CLK are inputted following theinitial state, initial first to eighth sampling data D₀-D₇ of the firstdigital signal I₀₁ are written and held in the first to eighth flip-flopsets 511-518 constituting the first storage section 510, respectively.Initial first to eighth sampling data d₀-d₇ of the second digital signalI₀₂ are written and held in the ninth to sixteenth flip-flop sets531-536 constituting the second storage section 530, respectively. Thedespreading codes C₇-C₀ are shifted to the first to eighth despreadingcode flip-flops 561-568 constituting the despreading code string shiftregister 560 and held therein, respectively. As a result, when the clockCLK is “1”, the sampling data D₀-D₇ of the first digital signal I_(o),are selected by means of the first to eighth selector circuit sets551-558, so that D₇×C₀+D₆×C₁+D₅×C₂+D₄×C₃+D₃×C₄+D₂×C₅+D₁×C₆+D₀×C₇ isobtained in the seventh adder 587. Thereby, a correlation value MFOUTbetween the initial 8 sampling data D₀-D₇ of the first digital signalI₀₁ and the 8-bit despreading code sequence C₇ C₆ C₅ C₄ C₃ C₂ C₁ C₀ isobtained and outputted to the outside through the output terminal 505.When the clock CLK is “0”, the sampling data d₀-d₇ of the second digitalsignal I₀₂ are selected by means of the first to eighth selector circuitsets 551-558, so that d₇×C₀+d₆×C₁+d₅×C₂+d₄×C₃+d₃×C₄+d₂×C₅+d₁×C₆+d₀×C₇ isobtained in the seventh adder 587. Thereby, a correlation value MFOUTbetween the initial 8 sampling data d₀-d₇ of the second digital signalI₀₂ and the 8-bit despreading code sequence C₇ C₆ C₅ C₄ C₃ C₂C₁ C₀ isobtained and outputted to the outside through the output terminal 505.As a result, an eight-times spread 16-order digital matched filter whichis constructed by using the FIR 2-times over-sampling interpolationdigital filter, like the digital matched filter according to the thirdembodiment shown in FIG. 8, can be realized.

In the digital matched filter according to the present embodiment, awrite selection circuit constructed by using a recursive tapped shiftregister which includes the first to eighth write selecting flip-flopsand the selector circuit as the write selection circuit 300 shown inFIG. 6 may be used in place of the first and second write selectioncircuits 520-540.

In the foregoing description, each despreading code constituting thedespreading code sequence C₇ C₆ C₅ C₄ C₃ C₂ C₁ C₀ is of 1 bit. However,the bit number of each despreading code constituting the despreadingcode sequence C₇ C₆ C₅ C₄ C₃ C₂ C₁ C₀ may sometimes be two or more(provided that the bit number of each despreading code is smaller thanthat of the digital signal I_(o)). For example, each despreading codemay be of 2 bits to indicate 1, 0, −1. When the bit number of eachdespreading code is two or more, a despreading code sequence shiftregister constructed of a recursive tapped shift register using 8flip-flop sets each including two or more flip-flops connected inparallel to each other may be used in place of the despreading codesequence shift register 560 shown in FIG. 9.

Each of the first to eighth multipliers 571-578 may not necessarily be amultiplier constructed of a logical circuit, and may be means foroutputting the same multiplication result (for example, a circuit whichoutputs an input signal as it is when the despreading code is “1”, andwhich inverts the code bit of the input signal and outputs a resultingsignal when the despreading code is “0” (multiplication of coefficient“−1”)).

(Fifth Embodiment)

A digital matched filter according to a fifth embodiment of the presentinvention is an eight-times spread 8-order digital matched filterconstructed by using memory devices. AS shown in FIG. 10, it comprises asignal input terminal 601, a clock input terminal 602, an addresscounter 650, a storage section 610 including first to eighth memories611-618, a despreading code sequence shift register 620 constructed byusing a recursive tapped shift register including first to eighthdespreading code flip-flops 621-628, first to eighth multipliers631-638, first to seventh adders 641-647, and an output terminal 605.Here, the addresses of the first to eighth memories 611-618 constitutingthe storage section 610 are defined as 0-th to seventh addresses,respectively.

A digital signal I_(o) generated by sampling an analog signal (spectrumspread signal) at a sampling frequency of 4.096 MHz is inputted to thesignal input terminal 601. The digital signal I_(o) is a 6-bit digitalsignal in terms of two's complement that is synchronous with a clock CLKof 4.096 MHz inputted from the clock input terminal 602. Data inputterminals of the first to eighth memories 611-618 constituting thestorage section 610 are applied with the digital signal I_(o). Addressinput terminals of the first to eighth memories 611-618 are applied withan output signal of the address counter 650.

The address counter 650 is a 3-bit counter which counts the clock CLKapplied through a clock input terminal C. For simplification ofexplanation, it is assumed that in the initial state, the output signalof the address counter 650 is rendered to be “111” which indicates theseventh address. When the initial clock CLK is applied to the clockinput terminal C of the address counter 650, the output signal of theaddress counter 650 is rendered to be “000” which indicates the 0-thaddress, so that the first memory 611 of the storage section 610 isplaced in writable condition. When the second clock CLK is applied tothe clock input terminal C of the address counter 650, the output signalof the address counter 650 is rendered to be “001” which indicates thefirst address, so that the second memory 612 is placed in writablecondition. Subsequently, the third to eighth memories 613-618 aresequentially placed in writable condition in a similar manner insynchronism with the clock CLK. Thereafter, when the ninth clock CLK isapplied to the clock input terminal C of the address counter 650, theoutput signal of the address counter 650 is rendered to be “000” whichindicates the 0-th address, so that the first memory 611 of the storagesection 610 is placed in writable condition. Accordingly, the digitalsignal I_(o) is sequentially fetched and held in the first to eighthmemories 611-618 constituting the storage section 610 in synchronismwith the clock CLK.

The first to eighth despreading code flip-flops 621-628 constituting thedespreading code sequence shift register 620 are written withdespreading codes of an 8-bit despreading code sequence C₇ C₆ C₅ C₄ C₃C₂ C₁ C₀, respectively. Hereinafter, for simplification of explanation,it is assumed that in the initial state, the despreading codes C₇-C₀ arestored in the first to eighth despreading code flip-flops 561-568,respectively. Clock input terminals C of the first to eighth despreadingcode flip-flops 621-628 are applied with the clock CLK, and thedespreading codes written in the first to eighth despreading codeflip-flops 621-628 are shifted from the first despreading code flip-flop621 toward the eighth despreading code flip-flop 628 in synchronism withthe clock CLK. It is to be noted that a despreading code which has beenshifted to the eighth despreading code flip-flop 628 is shifted to thefirst despreading code flip-flop 621 in synchronism with the next clockCLK. Thereby, the despreading code C₀-C₇ are outputted from the first toeighth despreading code flip-flops 621-628 while being shiftedsequentially in synchronism with the clock CLK. Each of the first toeighth multipliers 631-638 is a multiplier for 6 bits×1 bit, and outputsan output signal of 6 bits. In the first to eighth multipliers 631-638,multiplication operations of the digital signal I_(o) (6 bits) outputtedfrom the first to eighth memories 611-618 by the despreading codes (1bit) outputted from the first to eighth despreading code flip-flops621-628 are carried out, respectively. When the despreading codeindicates “0”, multiplication operations of the output signals of thefirst to eighth memories 611-618 by “−1” are carried out in themultipliers 631-638. The procedure for multiplication in the multipliers631-638 will be described hereunder.

In the first operation state, a first sampling data D₀ of the digitalsignal I_(o) is inputted to the signal input terminal 601 in synchronismwith the clock CLK, and the clock CLK is applied to the clock inputterminal C of the address counter 650. As a result, the output signal ofaddress counter 650 is rendered to be “111” indicative of the seventhaddress in the initial state is rendered to be “000” indicative of the0-th address. Consequently, the first sampling data D₀ is written andheld in the first memory 611. Also, the despreading code C₀ which hasbeen stored in the eighth despreading code flip-flop 628 of thedespreading code sequence shift register 620 in the initial state isshifted to the first despreading code flip-flop 621 in synchronism withthe clock CLK. As a result, multiplication of the first sampling data D₀by the despreading code C₀ is carried out in the first multiplier 631.Accordingly, an output signal indicative of a value of D₀×C₀ isoutputted from the first multiplier 631.

In the second operation state, a second sampling data D₁ of the digitalsignal I_(o) is inputted to the signal input terminal 201 in synchronismwith the clock CLK, and the clock CLK is applied to the clock inputterminal C of the address counter 650. As a result, the output signal ofthe address counter 650 is rendered to be “001” indicative of the firstaddress. Consequently, the second sampling data D₁ is written and heldin the second memory 612. At that time, in the first memory 611 of thestorage section 610, the first sampling data D₀ which has been writtenthereto in the first operation state is held as it is. The despreadingcodes stored in the despreading code sequence shift register 620 areshifted in synchronism with the clock CLK. As a result, the despreadingcode C₀ which has been shifted to the first despreading code flip-flop621 in the first operation state is shifted to the second despreadingcode flip-flop 622, and the despreading code Cl which has been stored inthe eighth despreading code flip-flop 628 is shifted to the firstdespreading code flip-flop 621. Consequently, multiplication of thesecond sampling data D₁ by the despreading code C₀ is carried out in thesecond multiplier 632, and multiplication of the first sampling data D₀by the despreading code C₁ is carried out in the first multiplier 631.Accordingly, an output signal indicative of a value of D₁×C₀ isoutputted from the second multiplier 632, and an output signalindicative of a value of D₀×C₁ is outputted from the first multiplier631. Subsequently, a similar operation is repeated until the seventhoperation state.

In the eighth operation state, an eighth sampling data D₇ of the digitalsignal I_(o) is inputted to the signal input terminal 601 in synchronismwith the clock CLK, and the clock CLK is applied to the clock inputterminal C of the address counter 650. As a result, the output signal ofthe address counter 650 is rendered to be “111” indicative of theseventh address. Consequently, the eighth sampling data D₇ is writtenand held in the eighth memory 618. At that time, in the first to seventhmemories 611-617 of the storage section 610, the first to seventhsampling data D₀-D₆ which have been written thereto up to the seventhoperation state are held, respectively. Also, the despreading codesstored in the despreading code sequence shift register 620 are shiftedin synchronism with the clock CLK, so that the despreading codes C₇-C₀are stored in the first to eighth despreading code flip-flops 621-628,respectively. Thereby, multiplication operations of the first to eighthsampling data D₀-D₇ of the digital signal I_(o), which are held in thefirst to eighth memories 611-618 of the storage section 610, by thedespreading codes C₇-C₀ which are stored in the first to eighthflip-flops 621-628 of the despreading code sequence shift register 620are carried out in the first to eighth multipliers 631-638,respectively. As a result, an output signal indicative of a value ofD₇×C₀ is outputted from the eighth multiplier 638, an output signalindicative of a value of D₆×C₁ is outputted from the seventh multiplier637, an output signal indicative of a value of D₅×C₂ is outputted fromthe sixth multiplier 636, an output signal indicative of a value ofD₄×C₃ is outputted from the fifth multiplier 635, an output signalindicative of a value of D₃×C₄ is outputted from the fourth multiplier634, an output signal indicative of a value of D₂×C₅ is outputted fromthe third multiplier 633, an output signal indicative of a value ofD₁×C₆ is outputted from the second multiplier 632, and an output signalindicative of a value of D₀×C₇ is outputted from the first multiplier631.

Through the above operation, multiplication operations necessary todetermine a correlation value between the initial 8-sampling data D₇ D₆D₅ D₄ D₃ D₂ D₁ D₀ of the digital signal I_(o) and the 8-bit despreadingcode sequence C₆ C₅ C₄ C₃ C₂ C₁ C₀ are all carried out.

In the ninth operation state, a ninth sampling data D₈ of the digitalsignal I_(o) is inputted to the signal input terminal 601 in synchronismwith the clock CLK, and the clock CLK is applied to the clock inputterminal C of the address counter 604. As a result, the output signal ofthe address counter 604 is rendered to be “000” indicative of the 0-thaddress. Consequently, the ninth sampling data De is written and held inthe first memory 611. At that time, in the second to eighth memories 612to 618 of the storage section 610, the second to eighth sampling dataD₁-D₇ which have been written thereto up to the eighth operation stateare held, respectively. Also, the despreading codes stored in thedespreading code sequence shift register 620 are shifted in synchronismwith the clock CLK, so that the despreading code C₀ is shifted to thefirst despreading code flip-flop 621, and the despreading codes C₇-C₁are shifted to the second to eighth despreading code flip-flops 622-628,respectively. Thereby, multiplication of the ninth sampling data D. ofdigital signal I_(o) held in the first memory 611 of the storage section610 by the despreading code C₀ shifted to the first despreading codeflip-flop 621 of the despreading code sequence shift register 620 iscarried out in the first multiplier 631, and multiplication operationsof the second to eighth sampling data D₁-D₇ of digital signal I_(o) heldin the second to eighth memories 612-618 by the despreading codes C₇-C₁shifted to the second to eighth despreading code flip-flops 622-628 ofthe despreading code sequence shift register 620 are carried out in thesecond to eighth multipliers 632-638, respectively. As a result, anoutput signal indicative of a value of D₈×C₀ is outputted from the firstmultiplier 631, an output signal indicative of a value of D₇×C₁ isoutputted from the eighth multiplier 638, an output signal indicative ofa value of D₆×C₂ is outputted from the seventh multiplier 637, an outputsignal indicative of a value of D₅×C₃ is outputted from the sixthmultiplier 636, an output signal indicative of a value of D₄×C₄ isoutputted from the fifth multiplier 635, an output signal indicative ofa value of D₃×C₅ is outputted from the fourth multiplier 634, an outputsignal indicative of a value of D₂×C₆ is outputted from the thirdmultiplier 633, and an output signal indicative of a value of D₁×C₇ isoutputted from the second multiplier 632.

As a result, multiplication operations necessary to determine acorrelation value between the 8-sampling data D₈ D₇ D₆ D₅ D₄ D₃ D₂ D₁,which is one sampling after the initial 8-sampling data D₇ D₆ D₅ D₄ D₃D₂ D₁ Dot by the 8-bit despreading code sequence C₇ C₆ C₅ C₄ C₃ C₂ C₁ C₀are all carried out. Subsequently, a similar operation is repeated.

Each of the first to fourth adders 641-644 is an adder for 6 bits+6bits, and outputs an output signal of 7 bits. Each of the fifth andsixth adders 645 and 646 is an adder for 7 bits+7 bits, and outputs anoutput signal of 8 bits. The seventh adder 647 is an adder for 8 bits+8bits, and outputs an output signal of 9 bits. In the first adder 641,addition of the output signal (6 bits) of the first multiplier 631 andthe output signal (6 bits) of the second multiplier 632 is carried out.In the second adder 642, addition of the output signal (6 bits) of thethird multiplier 633 and the output signal (6 bits) of the fourthmultiplier 634 is carried out. In the third adder 643, addition of theoutput signal (6 bits) of the fifth multiplier 635 and the output signal(6 bits) of the sixth multiplier 636 is carried out. In the fourth adder644, addition of the output signal (6 bits) of the seventh multiplier637 and the output signal (6 bits) of the eighth multiplier 638 iscarried out. In the fifth adder 645, addition of the output signal (7bits) of the first adder 641 and the output signal (7 bits) of thesecond adder 642 F>t=is carried out. In the sixth adder 646, addition ofthe output signal (7 bits) of the third adder 643 and the output signal(7 bits) of the fourth adder 644 is carried out. In the seventh adder647, addition of the output signal (8 bits) of the fifth adder 645 andthe output signal (8 bits) of the sixth adder 646 is carried out. As aresult, a correlation value MFOUT between the digital signal I_(o) andthe despreading code sequence C₇ C₆ C₅ C₄ C₃ C₂ C₁ C₀ is obtained andoutputted to the outside through the output terminal 605.

In the foregoing description, each despreading code constituting thedespreading code sequence C₇ C₆ C₅ C₄ C₃ C₂ C₁ C₀ is of 1 bit. However,the number of bits of each despreading code constituting the despreadingcode sequence C₇ C₆ C₅ C₄ C₃ C₂ C₁ C₀ may sometimes be two or more(provided that the bit number of each despreading code is smaller thanthat of the digital signal I_(o)). For example, each despreading codemay be of 2 bits to indicate 1, 0, −1. When the bit number of eachdespreading code is two or more, a despreading code sequence shiftregister constructed of a recursive tapped shift register using 8flip-flop sets each including two or more flip-flops connected inparallel to each other may be used in place of the despreading codesequence shift register 620 shown in FIG. 10.

Each of the first to eighth multipliers 631-638 may not necessarily be amultiplier constructed of a logical circuit but may be means foroutputting the same multiplication result (for example, a circuit whichoutputs an input signal as it is when the despreading code is “1”, andwhich inverts the code bit of the input signal and outputs a resultingsignal when the despreading code is “0” (multiplication of coefficient−1)).

When an eight-times spread 16-order digital matched filter isconstructed by using the FIR 2-times over-sampling interpolation digitalfilter as shown in FIG. 8, a storage section including 16 memories maybe used in place of the storage section 410, and a counter forsequentially designating addresses of the 16 memories may be used inplace of the write selection circuit 430.

When a digital matched filter is constructed which determines acorrelation value between the over-sampled digital signal as shown inFIG. 9 and the despreading code sequence, two storage sections eachincluding 8 memories may be used in place of the first and secondstorage sections 510 and 530, and two counters for sequentiallydesignating addresses of the 8 memories of the 2 storage sections may beused in place of the first and second write selection circuits 520 and530.

INDUSTRIAL APPLICABILITY

As has been described hereinbefore, in the digital matched filter of thepresent invention, consumption power can be reduced more greatly than inthe conventional matched filter, and the filter can be constructed ofonly the digital circuits. Accordingly, by utilizing the digital matchedfilter of the present invention, LSI formation can be facilitatedtogether with the peripheral circuit for digital signal processing andfor example, the receiver for spectrum spread communication can bereduced in size.

What is claimed is:
 1. A digital matched filter for determining acorrelation value between an N-bit digital signal, which is synchronouswith a clock, and a digital code sequence which includes M digitalcodes, comprising: a) first to M-th digital signal storing means appliedwith said N-bit digital signal; b) digital write selection means forsequentially selecting said first to M-th digital signal storing meansone by one in synchronism with said clock to store said N-bit digitalsignal in the selected digital signal storing means; c) a recursiveshift register for digital code sequence having first to M-th stages ofcode flip-flops connected in cascade, and being operative in synchronismwith said clock, wherein said M digital codes are stored in said firstto M-th stages of code flip-flops, respectively, and an output terminalof said M-th stage of code flip-flop is connected to an input terminalof said first stage of code flip-flop; d) first to M-th digitalmultiplication means for multiplying output signals of said first toM-th digital signal storing means by output signals of said first toM-th stages of code flip-flops, respectively; and e) digital additionmeans for adding output signals of said first to M-th digitalmultiplication means.
 2. A digital matched filter according to claim 1,wherein each of said first to M-th digital signal storing means includesN flip-flops which are connected in parallel and are operative insynchronism with said clock; said digital write selection meansincludes: a write selecting recursive shift register having first toM-th stages of write selecting flip-flops connected in cascade, andbeing operative in synchronism with said clock, wherein an output signalof said M-th stage of write selecting flip-flop being applied to saidfirst stage of write selecting flip-flop; and upon start of operation, asignal for selecting said digital signal storing means is stored indesired one of said first to M-th stages of write selecting flip-flops.3. A digital matched filter according to claim 1, wherein each of saidfirst to M-th digital signal storing means includes N flip-flops whichare connected in parallel and are operative in synchronism with saidclock; and said digital write selecting means includes: first to M-thstages of write selecting flip-flops connected in cascade, reset beforestart of operation, and operated in synchronism with said clock afterstart of operation; and a digital selection circuit outputting a signalfor selecting said digital signal storing means to said first stage ofwrite selecting flip-flop during only a period shorter than one periodof said clock after start of operation, and outputting an output signalof said M-th stage of write selecting flip-flop to said first stage ofwrite selecting flip-flop after said period has elapsed.
 4. A digitalmatched filter according to claim 1, wherein said first to M-th digitalsignal storing means include first to M-th memories of N bits, and saiddigital write selecting means includes an address counter which countssaid clock to sequentially output addresses of said first to M-thmemories in synchronism with said clock.
 5. A digital matched filter fordetermining a correlation value between an N-bit digital signal, whichis over-sampled by a first clock having a frequency which is m-times aslarge as a second clock, and a digital code sequence which includes Mdigital codes, comprising: a) m×M digital signal storing means appliedwith said N-bit digital signal; b) digital write selecting means forsequentially selecting said m×M digital signal storing means one by onein synchronism with said first clock to store said N-bit digital signalin the selected digital signal storing means; c) first to M-th digitalselection means dividing said m×M digital signal storing means by m todivide said m×M digital signal storing means into M blocks tosequentially select and output output signals of said m digital signalstoring means included in said M blocks within one period of said secondclock; d) a recursive shift register for digital code sequence havingfirst to M-th stages of code flip-flops which are connected in cascade,and being operative in synchronism with said second clock, wherein saidM digital codes are stored in said first to M-th staged of codeflip-flops, respectively, and an output terminal of said M-th stage ofcode flip-flop is connected to an input terminal of said first stage ofcode flip-flop; e) first to M-th digital multiplication means formultiplying output signals of said first to M-th digital selection meansby output signals of said first to M-th stages of code flip-flops,respectively; and f) digit al addition means for adding output signalsof said first to M-th digital multiplication means.
 6. A digital matchedfilter according to claim 5, wherein each of said m×M digital signalstoring means includes N flip-flops which are connected in parallel andare operative in synchronism with said first clock, and said digitalwrite selection means includes: a write selecting recursive shiftregister having first to (m×M)-th stages of write selecting flip-flopsconnected in cascade, and being operative in synchronism with said firstclock, wherein an output signal of said (m×M)-th stage of writeselecting flip-flop being applied to said first stage of write selectingflip-flop; and upon start of operation, a signal for selecting saiddigital signal storing means is stored in desired one of said first to(m×M)-th stages of write selecting flip-flops.
 7. A digital matchedfilter according to claim 5, wherein each of said m×M digital signalstoring means includes N flip-flops which are connected in parallel andare operative in synchronism with said first clock, and said digitalwrite selection means includes: first to (m×M)-th stages of writeselecting flip-flops connected in cascade, reset before start ofoperation, and operated in synchronism with said first clock after startof operation; and a digital selection circuit outputting a signal forselecting said digital signal storing means to said first stage of writeselecting flip-flop during only a period shorter than one period of saidfirst clock after start of operation, and outputting an output signal ofsaid (m×M)-th stage of write selecting flip-flop to said first stage ofwrite selecting flip-flop after said period has elapsed.
 8. A digitalmatched filter according to claim 5, wherein said m×M digital signalstoring means include m×M memories of N bits, and said digital writeselection means includes an address counter which counts said firstclock to sequentially output addresses of said m×M memories insynchronism with said first clock.
 9. A digital matched filter fordetermining a correlation value between an N-bit digital signal, whichis over-sampled by a first clock having a frequency which is m-times aslarge as a second clock, and a digital code sequence which includes Mdigital codes, comprising: a) serial/parallel conversion means forserial/parallel converting said digital signal serially inputted tooutput first to m-th digital signals in parallel; b) first to m-thdigital signal storage means applied with said first to m-th digitalsignals from said serial/parallel conversion means, respectively, andhaving each M memory units; c) digital write selection means forsequentially selecting said M memory units one by one in synchronismwith said second clock every said first to m-th digital storage means tostore said respective first to M-th digital signals in said respectiveselected memory units; d) first to M-th digital selection means forsequentially selecting and outputting output signals of said first tom-th digital signal storing means within one period of said second clockevery said M memory units, respectively; e) a recursive shift registerfor digital code sequence having first to M-th stages of code flip-flopswhich are connected in cascade, and being operative in synchronism withsaid second clock, wherein said M digital codes are stored in said firstto M-th stages of code flip-flops, respectively, and an output terminalof said M-th stage of code flip-flop is connected to an input terminalof said first stage of code flip-flop; f) first to M-th digitalmultiplication means for multiplying output signals of said first toM-th digital selection means by output signals of said first to M-thstages of code flip-flops, respectively; and g) digital addition meansfor adding output signals of said first to M-th digital multiplicationmeans.
 10. A digital matched filter according to claim 9, wherein eachof said M memory units of said first to m-th digital signal storingmeans includes N flip-flops which are connected in parallel and beingoperative in synchronism with said second clock; said digital writeselection means includes: first to m-th write selecting recursive shiftregisters each having first to M-th write selecting flip-flops connectedin cascade, and being operative in synchronism with said second clock,wherein an output signal of said M-stage of write selecting flip-flopbeing applied to said first stage of write selecting flip-flop; and uponstart of operation, signals for selecting said M memory units of saidfirst to m-th digital signal storing means are stored in desired ones ofsaid first to M-th stages of write selecting flip-flops of said first tom-th write selecting recursive shift registers, respectively.
 11. Adigital matched filter according to claim 9, wherein each of said Mmemory units of said first to m-th digital signal storing means includesN flip-flops which are connected in parallel and are operative insynchronism with said second clock, and said digital write selectionmeans includes: first to m-th write selecting shift registers eachhaving first to M-th stages of write selecting flip-flops connected incascade, reset before start of operation, and operated in synchronismwith said second clock after start of operation; and first to m-thdigital selection circuits for outputting signals for selecting said Mmemory units of said first to m-th digital signal storing means to saidfirst to M-th stages of write selecting flip-flops of said first to m-thwrite selecting shift registers, respectively, during only a shorterperiod than one period of said second clock after start of operation,and for outputting output signals of said M-th stages of write selectingflip-flops of said first to m-th write selecting shift registers to saidfirst stages of write selecting flip-flops of said respective first tom-th write selecting shift registers after said period has elapsed. 12.A digital matched filter according to claim 9, wherein each of said Mmemory units of said respective first to m-th digital signal storingmeans includes a digital signal storing memory of N bits, and saiddigital write selection means includes an address counter for countingsaid second clock to sequentially output addresses of said digitalsignal storing memories in synchronism with said second clock every saidfirst to m-th digital signal storing means.